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? freescale semiconductor, inc., 2004. all rights reserved. freescale semiconductor data sheet document number: scf5250ec rev. 1.1, 04/2005 table of contents 1 introduction this document provides an overview of the scf5250 coldfire ? processor and general descriptions of scf5250 features and its various modules. the scf5250 was designed as a system controller/decoder for compressed audio music players, especially portable and auto motive cd and hard disk drive players. the 32-bit coldfire core with enhanced multiply accumulate (emac) unit provides optimum performance and code density for the combination of control code and signal pr ocessing required for audio decoding and post processi ng, file management, and system control. low power features include a hardwired cd rom decoder, advanced 0.13um cmos process technology, 1.2v core power supply, and on-chip 128kbyte sram that enables windows media audio (wma) decoding without the need for external dram in cd applications. the scf5250 is also an excellent general purpose system controller with over 110 dhrystone 2.1 mips @ 120mhz performance at a very competitive price. the integrated peripherals and enhanced mac unit allow the 1 introduction..........................................................1 2 scf5250 block diagram ..... ........... ............ .........8 3 documentation ....................................................8 4 signal descriptions..............................................9 5 electrical characteristics ...................................21 6 pin-out and package information .....................38 scf5250 integrated coldfire? microprocessor data sheet
scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 introduction freescale semiconductor 2 scf5250 to replace both the microcontroll er and the dsp in certain appli cations. most peripheral pins can also be remapped as ge neral purpose i/o pins. 1.1 orderable part numbers 1.1.1 orderable part table 1.2 scf5250 features 1.2.1 coldfire v2 core the coldfire processor version 2 core consists of two independent, decoupled pipeline structures to maximize performance while minimizi ng core size.the instruction fetc h pipeline (ifp) is a two-stage pipeline for prefetching instructions . the prefetched instruction stream is then gated into the two-stage operand execution pipeline (oep), whic h decodes the instruction, fetches the required operands, and then executes the required function. because the ifp and oep pipelines are decoupled by an instruction buffer that serves as a fifo queue, the ifp can prefetch in structions in advance of their actual use by the oep, which minimizes time stalled waiting for instructions . the oep is implemented in a two-stage pipeline featuring a traditional risc data path with a dual-read -ported register file feed ing an arithmetic/logic unit (alu). 1.2.2 dma controller the scf5250 provides four fully programmable dma channels for quick data transfer. single and dual address mode is supported with th e ability to program bursting and cycle stealing. data transfer is selectable as 8, 16, 32, or 128-bits . packing and unpacking is supported. two internal audio channels and the dual uart can be used with the dma channels. all channels can perform memory to memory transfers. the dma controller has a user-sel ectable, 24- or 16-bit counter and a programmable dma exception handler. external requests are not supported. table 1. orderable part numbers orderable part number maximum clock frequency package type operating temperature range part status scf5250pv120 120 mhz 144 pin qfp -20 c to 70 c leaded scf5250ag120 120 mhz 144 pin qfp -20 c to 70 c lead free scf5250cpv120 120 mhz 144 pin qfp -40 c to 85 c leaded scf5250cag120 120 mhz 144 pin qfp -40 c to 85 c lead free SCF5250VM120 120 mhz 196 ball mapbga -20 c to 70 c lead free
introduction scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 freescale semiconductor 3 1.2.3 enhanced multiply and accumulate module (emac) the integrated emac unit provides a common set of dsp operations and enhances the integer multiply instructions in the coldfire architecture. the em ac provides functionality in three related areas: 1. faster signed and unsigned integer multiplies 2. new multiply-accumulate operations supporting signed and unsigned operands 3. new miscellaneous register operations multiplies of 16x16 and 32x32 wi th 48-bit accumulates are supported in addition to a full set of extensions for signed and unsigned integers pl us signed, fixed-point fractional input operands. the emac has a single-clock issue for 32x32-bit multiplication inst ructions and implements a four-stage execution pipeline. 1.2.4 instruction cache the instruction cache impr oves system performance by providing cached instructi ons to the execution unit in a single clock. the scf5250 proce ssor uses a 8k-byte, di rect-mapped instructi on cache to achieve 107 mips at 120 mhz. the cache is accesse d by physical addresses, where each 16-byte line consists of an address tag and a valid bit. the inst ruction cache also includes a burstin g interface for 16-bit and 8-bit port sizes to quickly fill cache lines. 1.2.5 internal 128-kbyte sram the 128-kbyte on-chip sram is available in two banks, sram0 (64k) and sr am1 (64k). it provides one clock-cycle access for the coldfire core. this sr am can store processor stack and critical code or data segments to maximize performance. memory in sr am1 can be accessed under dma. 1.2.6 sdram controller the scf5250 sdram controller provides a glueless interface for one bank of sdram up to 32 mb (256 mbits). the controller supp orts a 16-bit data bus. a unique addres sing scheme allows for increases in system memory size without rerout ing address lines and re wiring boards. the contro ller operates in page mode, non-page mode, and burst-p age mode and supports sdrams. 1.2.7 system interface the scf5250 provides a glueless inte rface to 16-bit port si ze sram, rom, and peri pheral devices with independent programmable c ontrol of the assertion and negation of chip-select and write-enable signals. the scf5250 also supports bursting roms. 1.2.8 external bus interface the bus interface controller transfers informati on between the coldfire core or dma and memory, peripherals, or other device s on the external bus. the external bus in terface provides 23 bits of address bus
scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 introduction freescale semiconductor 4 space, a 16-bit data bus, output enable, and read/write signals. this interface implements an extended synchronous protocol that supports bursting operations. 1.2.9 serial audio interfaces the sc5250 digital audio interface provi des three serial philips iis/sony eiaj interfaces. one interface is a 4-pin (1 bit clock, 1 word clock, 1 data in, 1 data out), the other two interfaces are 3-pin (1 bit clock, 1 word clock, 1 data in or out). the serial in terfaces have no limit on minimum sampling frequency. maximum sampling frequency is determined by maxi mum frequency on bit clock input. this is 1/3 the frequency of the internal system clock. 1.2.10 iec958 digital audio interfaces the scf5250 has one digital audio i nput interface, and one digital a udio output interface. the single output carries the consumer ?c? channel. 1.2.11 audio bus the audio interfaces connect to an inte rnal bus that carries all audio data. each receiver places its received data on the audio bus and eac h transmitter takes data from the audi o bus for transmission. each transmitter has a source select register. in addition to the audio interfaces, there are six cpu accessi ble registers connected to the audio bus. three of these registers allow data reads from the audio bus and allow select ion of the audio source. the other three register provide a write path to the audio bus and can be selected by transmitters as the audio source. through these registers, the cpu has acces s to the audio samples for processing. audio can be routed from a receiver to a transmitte r without the data being processed by the core so the audio bus can be used as a digital audio data switc h. the audio bus can also be used for audio format conversion. 1.2.12 cd-rom encoder/decoder the scf5250 is capable of proce ssing cd-rom sectors in hardware . processing is compliant with cd-rom and cd-rom xa standards. the cd-rom decoder performs fo llowing functions in hardware: ? sector sync recognition ? descrambling of sectors ? verification of the crc checksum for mode 1, mode 2 form 1, and mode 2 form 2 sectors ? third-layer error corr ection is not performed the cd-rom encoder performs fo llowing functions in hardware: ? sector sync recognition ? scrambling of sectors
introduction scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 freescale semiconductor 5 ? insertion of the crc checksum for mode 1, mode 2 form 1, and mode 2 form 2 sectors. ? third-layer error encoding needs to be done in software. this can use approximately 5-10 mhz of performance for single-speed. 1.2.13 dual uart module two full-duplex uarts with independent receive and tr ansmit buffers are in this module. data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity , and up to 2 stop bits in 1/16 increments. four-byte receive buffers and two-byte transm it buffers minimize cpu service calls. the dual uart module also provides several error-detection and maskable-i nterrupt capabilities. modem support includes request-to-send (rts ) and clear-to-send (cts ) lines. the system clock provides the clocking function from a programmable prescaler . you can select full duplex, auto-echo loopback, local loopback, and remote loopback modes. the programmable dual uarts can interrupt the cpu on various normal or error-condition events. 1.2.14 queued serial peripheral interface qspi the qspi module provides a serial pe ripheral interface with queued tran sfer capability. it supports up to 16 stacked transfers at a time, making cpu interventi on between transfers unnecess ary. transfers of up to 15 mbits/second are possible at a cpu clock of 120 mhz. the qspi supp orts master mode operation only. 1.2.15 timer module the timer module includes tw o general-purpose timers, e ach of which contains a free-running 16-bit timer. timer0 has an external pin tout0, which can be used in output compare mode. this mode triggers an external signal or interrupt s the cpu when the timer re aches a set value, and can also generate waveforms on tout0. the timer unit has an 8-bit prescaler that allows programming of the clock input frequency, which is derived from the system clock. in a ddition to the 1 and 16 clock deri ved from the bus clock (cpu clock / 2), the programmable timer-output pins either generate an activ e-low pulse or toggle the outputs. 1.2.16 ide and smartmedia interfaces the scf5250 system bus allows connection of an ide ha rd disk drive or smartmedia flash card with a minimum of external hardware. the external hardware consists of bus buffers fo r address and data and are intended to reduce the load on the bus and prevent sdram and flash accesses to propagate to the ide bus. the control si gnals for the buffers are generated in the scf5250. 1.2.17 analog/digital converter (adc) the six channel adc is a based on the sigma-delta concept with 12- bit resolution. both the analogue comparator and digital s ections of the adc are provided internal ly. an external integrator circuit (resistor/capacitor) is required, which is driven by the adc output. a software inte rrupt is provided when the adc measurement cycle is complete.
scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 introduction freescale semiconductor 6 1.2.18 i 2 c module the two-wire i 2 c bus interface, which is compliant with the philips i 2 c bus standard, is a bidirectional serial bus that exchanges data between devices. the i 2 c bus minimizes the interconnection between devices in the end system and is best suited for applications that need occasional bursts of rapid communication over short distances among several devices. bus cap acitance and the number of unique addresses limit the maximum communication length a nd the number of devices that can be connected. 1.2.19 chip-selects up to four programmable chip-select outputs provide signals that enable glueless connection to external memory and peripheral circuits. the base address, access permissions a nd automatic wait-state insertion are programmable with configurat ion registers. these signals al so interface to 16-bit ports. cs0 is active after reset to provide boot-up from external flash/rom. 1.2.20 gpio interface a total of 60 general purpose input s and 57 general purpose outputs are available. these are multiplexed with various other signals. seven of the gpio i nputs have edge sensitive interrupt capability. 1.2.21 interrupt controller the interrupt controller provides user-programmable control of a to tal of 57 interrupts. there are 49 internal interrupt sources. in add ition, there are 7 gpios where interrupts can be generated on the rising or falling edge of the pin. all interrupts are au tovectored and interrupt levels are programmable. 1.2.22 jtag to help with system diagnostics and manufac turing testing, the scf 5250 includes dedicated user-accessible test logic that co mplies with the ieee 1149.1a standard for boundary scan testability, often referred to as joint test action group, or jt ag. for more information, refer to the ieee 1149.1a standard. freescale provides bsdl files for jtag testing. 1.2.23 system debug interface the coldfire processor core debug interface s upports real-time instruct ion trace and debug, plus background-debug mode. a background-debug mode (bdm) interface provides system debug. in real-time instruction tra ce, four status lines provide information on processor activity in real time (pst pins). a four-bit wide debug data bus (ddata) displays operand data and change-of-flow addresses, which helps track the machin e?s dynamic execution path.
introduction scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 freescale semiconductor 7 1.2.24 crystal and on-chip pll typically, an external 16.92 mhz or 33.86 mhz clock input is used for cd r/w applications, while an 11.2896 mhz clock is more practical for portable cd player applications. however, the on-chip programmable pll, which generates the processor clock, allows the use of almost any low frequency external clock (5-35 mhz). two clock outputs (mclk1 and mc lk2) are provided for use as audio master clock. the output frequencies of both outputs are progra mmable to fxtal, fxtal/2, fxtal/3, and fxtal/4. the fx tal/3 option is only available when the 33.86 mhz crystal is connected. the scf5250 supports vco operation of the oscillator by means of a 16-bit pulse density modulation output. using this mode, it is possibl e to lock the oscillator to the fr equency of an incoming iec958 or iis signal. the maximum trim depends on the type and de sign of the oscillator. typically a trim of +/- 100 ppm can be achieved with a crystal oscillator and over +/- 1000 ppm with an lc oscillator. 1.2.25 boot rom the boot rom on the scf5250 serves to boot the cpu in designs which do not have external flash memory or rom. typically this occurs in systems which have a separate mcu to control the system, and/or the scf5250 is used as a stand-alone decoder. the scf5250 can be booted in one of three modes: ? external rom ? internal rom master mode ? boots from i2c, spi, or ide ? internal rom slave mode ? boots from i2c or uart 1.2.26 voltage regulator the scf5250 contains an on-chip line ar regulator that generates 1.2v fr om a 3.3v input. the regulator is self-contained and drives th e 1.2v core voltage out on on e pin that can be used to power the core supply pins at the board level. in battery powered portable appl ications, it is recommende d that an external dc-dc converter be used to generate the 1.2v co re voltage to minimi ze power consumption.
scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 scf5250 block diagram freescale semiconductor 8 2 scf5250 block diagram figure 1. scf5250 block diagram 3 documentation table 2 lists the documents that provide a complete de scription of the scf5250 and are required to design properly with the part. documentat ion is available from a local fr eescale distributor, a freescale semiconductor sales office, a freescal e literature distributi on center, or through the freescale dsp home page on the internet; http://e-www.freescale.c om/ (the source for the latest information). emac v2 coldfire ? core system bus controller sdram ctr & chip selects qspi i 2 c x2 dmas / timers jtag 12-bit adc ide interface gpi/o pll bdm 128k sram 8k i-cache flash media int boot rom oscillator cd rom block encode & decode i 2 s rx x3 i 2 s tx x2 uart x2 spdif tx spdif rx 1.2v regulator
signal descriptions scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 freescale semiconductor 9 . 4 signal descriptions 4.1 introduction this section describes the scf5250 input and output si gnals. the signal descripti ons as shown in table 2-a are grouped according to relevant functionality. table 2. scf5250 documentation document name description order number cfprm/d coldfire family programmer?s reference manual cfprm/d coldfire2um version 2/2m coldfire core processor user?s manual coldfire2um/d coldfire2umad version 2/2m coldfire core processor user?s manual addendum coldfire2umad/d scf5250um scf5250 user?s manual scf5250um/d table 3. scf5250 signal index signal name mnemonic function input/ output reset state address a[24:1] a[23]/gpo54 24 address lines, address line 23 multiplexed with gpo54 and address 24 is multiplexed with a20 (sdram access only). out x read-write control r/w bus write enable - indicates if read or write cycle in progress out h output enable oe output enable for asynchronous memories connected to chip selects out negated data d[31:16] data bus used to transfer word data in/out hi-z synchronous row address strobe sdras /gpio59 row address strobe for external sdram. out negated synchronous column address strobe sdcas /gpio39 column address strobe for external sdram out negated sdram write enable sdwe /gpio38 write enable for external sdram out negated sdram upper byte enable sdudqm /gpo53 indicates during wr ite cycle if high byte is written out sdram lower byte enable sdldqm /gpo52 indicates during write cycle if low byte is written out sdram chip selects sd_cs0 /gpio60 sdram chip select in/out negated sdram clock enable bclke/gpio63 sdram clock enable out system clock bclk/gpio40 sdram clock output in/out
scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 signal descriptions freescale semiconductor 10 isa bus read strobe ide-dior /gpio31 (cs2) there is 1 isa bus read strobe and 1 isa bus write strobe. they allow connection of one independent isa bus peripherals, e.g. an ide slave device. in/out isa bus write strobe ide-diow /gpio32 (cs2) in/out isa bus wait signal ide-iordy /gpio33 isa bus wait line - available for both busses in/out chip selects[2:0] cs0 /cs4 cs1 /qspi_cs3/gpio28 enables peripherals at programmed addresses. cs[ 0] provides boot rom selection out in/out negated buffer enable 1 bufenb1 /gpio29 two programmable buffer enables allow seamless steering of external buffers to split data and address bus in sections. in/out buffer enable 2 bufenb2 /gpio30 in/out transfer acknowledge ta /gpio12 transfer acknowledge signal in/out wake up wake_up /gpio21 wake-up signal input in serial clock line sc l0/sdata1_bs1/gpio41 scl1/txd1/gpio10 clock signal for dual i 2 c module operation in/out serial data line sda0/sdata3/gpio42 sda1/rxd1/gpio44 serial data port for second i 2 c module operation in/out receive data sda1/rxd1/gpio44 rxd0/gpio46 signal is receive serial data input for duart in transmit data scl1/txd1/gpio10 txd0/gpio45 signal is transmit serial data output for duart out request-to-send ddata3/rts0 /gpio4 ddata1/rts1 /sdata2_bs2/gpio2 duart signals a ready to receive data query out clear-to-send ddata2/ctso /gpio3 ddata0/cts1 /sdata0_sdio1/gpio1 signals to duart that data can be transmitted to peripheral in timer output sdatao1/tout0/gpio18 capa ble of output waveform or pulse generation out iec958 inputs ebuin1/gpio36 ebuin2/sclk_out/gpio13 ebuin3/cmd_sdio2/gpio14 qspi_cs0/ebuin4/gpio15 audio interfaces iec958 inputs in iec958 outputs ebuout1/gpio37 qspi_cs1/ebuout2/gpio16 audio interfaces iec958 outputs out serial data in sdatai1/gpio17 sdatai3/gpio8 audio interfaces serial data inputs in serial data out sdatao1/tout0/gpio18 sdatao2/gpio34 audio interfaces serial data outputs in/out out word clock lrck1/gpio19 lrck2/gpio23 lrck3/gpio43/audio_clock audio interfaces serial word clocks in/out bit clock sclk1/gpio20 sclk2/gpio22 sclk3/gpio35 audio interfaces serial bit clocks in/out table 3. scf5250 signal index (continued) signal name mnemonic function input/ output reset state
signal descriptions scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 freescale semiconductor 11 serial input ef/gpio6 error flag serial in in/out serial input cflg/gpio5 c- flag serial in in/out subcode clock rck/qspi_din/qspi_dout/ gpio26 audio interfaces subcode clock in/out subcode sync qspi_dout/sfsy/gpio27 audio interfaces subcode sync in/out subcode data qspi_clk/subr/gpio25 audio interfaces subcode data in/out clock frequency trim xtrim/gpio0 clock trim control out audio clocks out mclk1/gpio11 qspi_cs2/mclk2/gpio24 dac output clocks out audio clock in lrck3/gpio43/audio_ clock optional audio clock input memorystick/ securedigita l interface ebuin3/cmd_sdio2/gpio14 secure digital command lane memorystick interface 2 data i/o in/out ebuin2/sclk_out/gpio13 clock out for both memorystick interfaces and for secure digital in/out ddata0/cts1 /sdata0_sdio1/gpio1 securedigital serial data bit 0 memorystick interface 1 data i/o in/out scl0/sdata1_bs1/gpio41 securedigital serial data bit 1 memorystick interface 1 strobe in/out ddata1/rts1 /sdata2_bs2/gpio2 securedigital serial data bit 2 memorystick interface 2 strobe reset output signal in/out sda0/sdata3/gpio42 securedigital serial data bit 3 in/out adc in adin0/gpi52 adin1/gpi53 adin2/gpi54 adin3/gpi55 adin4/gpi56 adin5/gpi57 analog to digital converter input signals in adc out adref adout/sclk4/gpio58 analog to digital convertor output signal. connect to adref via integrator network. in/out qspi clock qspi_clk/subr/gpio25 qspi clock signal in/out qspi data in rck/qspi_din/qspi_d out/gpio26 qspi data input in/out qspi data out rck/qspi_din/qspi_dout/gpio26 qspi_dout/sfsy/gpio27 qspi data out in/out qspi chip selects qspi_cs0/ebuin4/gpio15 qspi_cs1/ebuout2/gpio16 qspi_cs2/mclk2/gpio24 cs1 /qspi_cs3/gpio28 qspi chip selects in/out crystal in crin crystal input in crystal out crout crystal out out reset in rsti proce ssor reset input in freescale test mode test[2:0] test pins. in linear regulator output linout outputs 1.2 v to supply core out table 3. scf5250 signal index (continued) signal name mnemonic function input/ output reset state
scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 signal descriptions freescale semiconductor 12 4.2 gpio many pins have an optional gpio function. ? general purpose input is always ac tive, regardless of state of pin. ? general purpose output or primar y output is determined by the appropriate setting of the pin multiplex control registers, gpio-funct ion, gpio1-function and pin-config. ? at power-on reset, all pins ar e set to their primary function. 4.3 scf5250 bus signals these signals provide the extern al bus interface to the scf5250. linear regulator input linin input, typically i/o supply (3.3v) in linear regulator ground lingnd high impedance hi-z assertion tri-states all output signal pins. in debug data ddata0/cts1 /sdata0_sdio1/gpio1 ddata1/rts1 /sdata2_bs2/gpio2 ddata2/cts0 /gpio3 ddata3/rts0 /gpio4 displays captured processor data and break-point status. in/out hi-z processor status pst0/gpio50 pst1/gpio49 pst2/intmon2/gpio48 pst3/intmon1/gpio47 indicates internal processor status. in/out hi-z processor clock pstclk/gpio51 processor clock output out test clock tck clock signal for ieee 1149.1a jtag. in test reset/development serial clock trst /dsclk multiplexed signal that is asynchronous reset for jtag controller. clock input for debug module. in test mode select/ break point tms/bkpt multiplexed signal that is test mode select in jtag mode and a hardware break-point in debug mode. in test data input / development serial input tdi/dsi multiplexed serial input for the jtag or background debug module. in test data output/development serial output tdo/dso multiplexed serial output for the jtag or background debug module. out table 3. scf5250 signal index (continued) signal name mnemonic function input/ output reset state
signal descriptions scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 freescale semiconductor 13 4.3.1 address bus ? the address bus provides the addr ess of the byte or most significa nt byte of the word or longword being transferred.the a ddress lines also serve as the dram address pins, providing multiplexed row and column address signals. ? bits 23 down to 1 and 24 of the a ddress are available. a24 is inte nded to be used with 256 mbit dram?s. signals are named: ? a[23:1] ? a20/24 4.3.2 read-write control this signal indicates during any bus cycle whether a read or write is in progress. a low is write cycle and a high is a read cycle. 4.3.3 output enable the oe signal is intended to be connected to the out put enable of asynchronous memories connected to chip selects. during bus read cycles, the coldfire processor will drive oe low. 4.3.4 data bus the data bus (d[31:16]) is bi-dir ectional and non-multiplexed. data is registered by the scf5250 on the rising clock edge. the data bus uses a default conf iguration if none of the chip-selects or dram bank match the address decode. al l 16 bits of the data bus are driven during writes, re gardless of port width or operand size. 4.3.5 transfer acknowledge the ta /gpio12 pin is the transfer acknowledge signal. 4.4 sdram controller signals the following sdram signals provide a glueless interface to external sdram. an sdram width of 16 bits is supported and can access as much as 32mb of memory. adrams are not supported. table 4. sdram controller signals sdram signal description synchronous dram row address strobe the sdras /gpio59 active low pin provides a seamless interface to the ras input on synchronous dram synchronous dram column address strobe the sdcas /gpio39 active low pin provides a seamless interface to cas input on synchronous dram. synchronous dram write the sdwe /gpio38 active-low pin is asserted to signify that a sdram write cycle is underway. this pin outputs logic ?1? during read bus cycles.
scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 signal descriptions freescale semiconductor 14 4.5 chip selects there are three chip select out puts on the scf5250 device. cs0 /cs4 and cs1 /qspi_cs3/gpio28 and cs2 which is associated with the ide interface read and write strobes - ide-dior and ide-diow. cs0 and cs4 are multiplexed. the scf5250 has the option to boot from an internal boot rom. the function of the cs0/cs4 pin is determined by the boot mode. when the device is booted from internal rom, the internal rom is accessed with cs0 (requi red for boot) and the cs0/cs4 pin is driven by cs4. when the device is booted from external rom / flash, the cs0/cs4 pin is driven by cs0 and the internal rom is disabled. the active low chip sel ects can be used to access asynchronous memories. the interface is glueless. 4.6 isa bus the scf5250 supports an isa bus. using the isa bu s protocol, reads and writes for one isa bus peripheral is possible. ide-dior/ gpio31 and ide-diow /gpio32 are the read and write strobe. the peripheral can insert wait st ates by pulling ide-iordy/gpio33. cs2 is associated with th e ide-dior and ide-diow. 4.7 bus buffer signals as the scf5250 has a complicated slave bus, whic h allows sdram, asynchronous memories, and isa peripherals on the bus, it may become necessary to in troduce a buffer on the bus in certain applications. the scf5250 has a glueless interface to steer thes e bus buffers with two bus buffer output signals bufenb1 /gpio29 and bufenb2 /gpio30. 4.8 i 2 c module signals there are two i 2 c interfaces on this device. the i 2 c module acts as a two-wire, bidi rectional serial interface be tween the scf5250 processor and peripherals with an i 2 c interface (e.g., led controller, a-to-d converter, d-to-a converter). when synchronous dram chip enable the sd_cs0 /gpio60 active-low output signal is used during synchronous mode to route directly to the chip select of a sdram device. synchronous dram udqm and lqdm signals the dram byte enables udmq and ldqm are driven by the sdudqm/gpo53 and sdldqm/gpo52 byte enable outputs. synchronous dram clock the dram clock is driven by the bclk/gpio40 signal synchronous dram clock enable the bclke active high output signal is used during synchronous mode to route directly to the scke signal of external sdrams. this signal provides the clock enable to the sdram. table 4. sdram controller signals (continued) sdram signal description
signal descriptions scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 freescale semiconductor 15 devices connected to the i 2 c bus drive the bus, they will either driv e logic-0 or high-im pedance. this can be accomplished with an open-drain output. 4.9 serial module signals the following signals transfer se rial data between the two uart m odules and external peripherals. 4.10 timer module signals the following signal provides an external interface to timer0. table 5. i 2 c module signals i 2 c module signal description i 2 c serial clock the scl0/sdata1_bs1/gpio41 and scl1/txd1/gpio10 bidirectional signals are the clock signal for first and second i 2 c module operation. the i 2 c module controls this signal when the bus is in master mode; all i 2 c devices drive this signal to synchronize i 2 c timing. signals are multiplexed i 2 c serial data the sda0/sdata3/gpio42 and sda1/rxd1/gpio44 bidirectional signals are the data input/output for the first and second serial i 2 c interface. signals are multiplexed table 6. serial module signals serial module signal description receive data the rxd0/gpio46 and sda1/r xd1/gpio44 are the inputs on which serial data is received by the duart. data is sampled on rxd[1:0] on the rising edge of the serial clock source, with the least significant bit received first. transmit data the duart transmits serial data on the txd0/gpio45 and scl1/txd1/gpio10 output signals. data is transmitted on the falling edge of the serial clock source, with the least significant bit transmitted (lsb) first. when no data is being transmitted or the transmitter is disabled, these two signals are held hi gh. txd[1:0] are also held high in local loopback mode. request to send the ddata3/rts0/gp1 04 and ddata1/rts1/sdata2_bs2/gpio2 request-to-send outputs indicate to the peripheral device that the duart is ready to send data and requires a clear-to-send signal to initiate transfer. clear to send peripherals drive the ddata2/cts0/gpio3 and ddata0/cts1/sdata0_sdio1/gpio1 inputs to indicate to the scf5250 serial module that it can begin data transmission. table 7. timer module signals serial module signal description timer output the sdatao1/tout0/gpio18 programmable output pulse or toggle on various timer events.
scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 signal descriptions freescale semiconductor 16 4.11 serial audio interface signals the following signals provide the external audio interface. table 8. serial audio interface signals serial module signal description serial audio bit clock the sclk1/gpio20, sclk2/gpio22 and sclk3/gpio35, multiplexed pins can serve as general purpose i/os or serial audio bit clocks. as bit clocks, these bidirectional pins can be programmed as outputs to drive their associated serial audio (iis) bit clocks. alternately, these pins can be programmed as inputs when the serial audio bit clocks are driven internally. the functionality is programmed within the audio module. during reset, these pins are configured as input serial audio bit clocks. serial audio word clock the lrck1/gpio19, lrck2/gpio23 and lrck3/gpio43/audio_clock multiplexed pins can serve as general purpose i/os or serial audio word clocks. as word clocks, the bidirectional pins can be programmed as inputs to drive their associated serial audio word clock. alternately, these pins can be programmed as outputs when the serial audio word clocks are derived internally. the functionality is programmed within the audio module. during reset, these pins are configured as input serial audio word clocks. lrck3/gpio43/audio_clock can be used as the external audio clock input. if the core clock chosen to be non-audio specific. serial audio data in the sdatai1/gpio17 and sdatai3/gpio8 multiplexed pins can serve as general purpose i/os or serial audio inputs. as serial audio inputs the data is sent to interfaces 1and 3 respectively. during reset, the pins are configured as serial data inputs. serial audio data out sdato1/tout0/gpio18 and sdatao2/gpio34 multiplexed pins can serve as general purpose i/os or serial audio outputs. during reset, the pins are configured as serial data outputs. serial audio error flag the ef/gpio6 multiplexed pin can serve as general purpose i/os or error flag input. as error flag input , this pin will input the error flag delivered by the cd-dsp. ef/gpio6 is only relevant for serial interface sdatai1. serial audio cflg the cflg/gpio5 multiplex ed pin can serve as general purpose i/o or cflg input. as cflg input, the pi n will input the cflg flag delivered by the cd-dsp. cflg/gpio5 is only relevant for serial interface sdatai1.
signal descriptions scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 freescale semiconductor 17 4.12 digital audio interface signals 4.13 subcode interface there is a 3-line subcode interface on the scf5250. this 3-line subcode interface allows the device to format and transmit subcode in eiaj format to a cd channel encoder device. the three signals are described in table 10 . 4.14 analog to digital converter (adc) the adout signal on the adout/sclk4/gpio58 pin pr ovides the reference voltage in pwm format. this output requires an external integr ator circuit (resistor/capac itor) to convert it to a dc level to be input to the adref pin. the six ad inputs are each fed to their own comparat or. the reference input to each (adref) is then multiplexed as only one ad comparis on can be made at any one time. note to use the adinx as general purpos e inputs (rather th an there analogue function) it is necessary to generate a fixed comparator voltage level of vdd/2. this can be accomplished by a potential divider network connected to the adref pin. however in portabl e applications where stand-by power table 9. digital audio interface signals serial module signal description digital audio in the ebuin1/gpio36, ebuin2/sclk_out/gpio13, ebuin3/cmd_sdio2/gpio14, and qspi_cs0/ebuin4/gpio15 multiplexed signals can serve as general purpose input or can be driven by various digital audio (iec958) input sources. both functionalities are always active. input chosen for iec958 receiver is programmed within the audio module. input value on the 4 pins can always be read from the appropriate gpio register. digital audio out the ebuout1/gp io37 and qspi_cs1/ebuout2/gpio16 multiplexed pins can serve as general purpose i/o or as digital audio (iec958) output. ebuout1 is digi tal audio out for consumer mode, ebuout2 is digital audio out for professional mode. during reset, the pin is configured as a digital audio output. table 10. subcode interface signal signal name description rck/qspi_din/qspi_dout/gpio26 subcode clock input. when pin is used as subcode clock, this pin is driven by the cd channel encoder. qspi_dout/sfsy/gpio27 subcode sync output this signal is driven high if a subcode sync needs to be inserted in the efm stream. qspi_clk/subr/gpio25 subcode data output this signal is a subcode data out pin.
scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 signal descriptions freescale semiconductor 18 consumption is important the curren t taken by the divider network (in stand-by mode) could be ex cessive. therefore it is possible to generate a vdd/2 voltage by selecting sclk4 out put mode and feeding this clock signal (which is 50% duty cycle) through an extern al integration circuit. this would generate a voltage level equal to vdd/2 but would be disabled when stand-by mode was selected. 4.15 secure digital/ memorystick card interface the device has a versatile flash card interface that supports both secu redigital and memorystick cards. the interface can either support one s ecuredigital or two memorystick car ds. no mixing of card types is possible. table 11 gives the pin descriptions. 4.16 queued serial peripheral interface (qspi) the qspi interface is a high-speed serial interface allowing transmit and recei ve of serial data. pin descriptions are given in table 12 . table 11. flash memory card signals flash memory signal description ebuin2/sclkout/gpio13 clock out for both memorystick interfaces and for securedigital ebuin3/cmd_sdio2/gpio14 secure digital command line memorystick interface 2 data i/o ddatao/cts1 /sdata0_sdio1/gpio1 securedigital serial data bit 0 memorystick interface 1 data i/o scl0/sdata1_bs1/gpio41 securedigital serial data bit 1 memorystick interface 1 strobe ddata1/rts1 /sdata2_bs2/gpio2 securedigital serial data bit 2 memorystick interface 2 strobe reset output signal selection between reset function and sdata2_bs2 is done by programming pllcr register. sda0/sdata3/gpio42 securedigital serial data bit 3 table 12. queued serial peripheral interface (qspi) signals serial module signal description qspiclk/subr/gpio25 multiplexed signal iic interface clock or qspi clock output function select is d one via pllcr register. rck/qspidin/qspi_dout/gpio26 multiplexed signal iic interface data or qspi data input. function select is d one via pllcr register. rck/qspi_din/qspi_dout/gpio26 qspi_dout/sfsy/gpio27 qspi data output
signal descriptions scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 freescale semiconductor 19 4.17 crystal trim the xtrim/gpio0 output produces a pulse-density modulated phase/frequency difference signal to be used after low-pass filtering to control varicap-voltage to control cr ystal oscillation frequency. this will lock the crystal to the incoming digital audio signal. 4.18 clock out the mclk1/gpio11 and qspi_cs2/mclk2/gpio 24 can serve as dac clock outputs. when programmed as dac clock outputs, thes e signals are directly derived from the crystal osci llator or clock input (crin). 4.19 debug and test signals these signals interface with external i/o to provide processor debug and status signals. 4.19.1 test mode the test[2:0] inputs are used for various manufactur ing and debug tests. for normal mode test [2:1] should be ways be tied low. tes t0 should be set high for bdm debug mode and set low for jtag mode. 4.19.2 high impedance the assertion of hi_z will force all output drivers to a hi gh-impedance state. the timing on hi_z is independent of the clock. note jtag operation will override the hi_z pin. 4.19.3 processor clock output the internal pll generates this pstclk/gpio51 and out put signal, and is the processor clock output that is used as the timing reference for the de bug bus timing (ddata[3:0] and pst[3:0]). the pstclk/gpio51 is at the same fre quency as the core processor. qspics0/ebuin4gpio15 4 different qspi chip selects qspics1/ebuout2/gpio16 qspics2/mclk2/gpio24 cs1/qspics3/gpio28 table 12. queued serial peripheral interface (qspi) signals (continued) serial module signal description
scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 signal descriptions freescale semiconductor 20 4.19.4 debug data the debug data pins, ddata0/cts1/sdata0_sdi o1/gpio1, ddata1/rts1/sdata2_bs2/gpio2, ddata2/cts0/gpio3, and ddata3/rts0/gpio4, are four bits wide. this nibbl e-wide bus displays captured processor data and break-point status. 4.19.5 processor status the processor status pins, pst0/gpio50, pst1/gpio49, pst2/intmon/gpio48, and pst3/intmon/gpio47, indicate th e scf5250 processor status. du ring debug mode, the timing is synchronous with the processor clock (pstclk) and the status is not re lated to the current bus transfer. table 13 shows the encodings of these signals. . table 13. processor status signal encodings pst[3:0] definition (hex) (binary) $0 0000 continue execution $1 0001 begin execution of an instruction $2 0010 reserved $3 0011 entry into user-mode $4 0100 begin execution of pulse and wddata instructions $5 0101 begin execution of taken branch or synch_pc 1 $6 0110 reserved $7 0111 begin execution of rte instruction $8 1000 begin 1-byte data transfer on ddata $9 1001 begin 2-byte data transfer on ddata $a 1010 begin 3-byte data transfer on ddata $b 1011 begin 4-byte data transfer on ddata $c 1100 exception processing 2 $d 1101 emulator mode entry exception processing 2 $e 1110 processor is stopped, waiting for interrupt 2 $f 1111 processor is halted 2 rev. b enhancement. these encodings are asserted for multiple cycles.
electrical characteristics scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 freescale semiconductor 21 4.20 bdm/jtag signals the scf5250 complies with the ieee 1149.1a jtag testing standard. the jtag test pins are multiplexed with background debug pins. 4.21 clock and reset signals these signals configure the scf5250 and provide interface signals to the external system. 4.21.1 reset in asserting rsti causes the scf5250scf5250 to enter reset exception processing. when rsti is recognized, the data bus is tri-stated. 4.21.2 clock input scf5250 includes on -chip crystal osci llator. the crystal should be c onnected between crin and crout. an externally generated clock signal can also be us ed and should be connected directly to the crin pin. 4.22 wake-up signal to exit power down mode, apply a low level to the wake_up/gpio21 input pin. 4.23 on-chip linear regulator the scf5250 includes an on-chip linear regulator. th is regulator provides an 1.2 v output which is intended to be used to power the scf5250 core. three pins are associat ed with this function. linin, linout and lingnd. typically linin woul d be fed by the i/o (pad) supply (3.3 v) with separate filtering recommende d to provide some isolation between the i/o and the core. in portable solutions this linear re gulator may not be efficient enough and in this case we would expect the 1.2 v supply to be generated externally, po ssibly by a highly effici ent dc-dc convertor. if not used leave pins not connected. 5 electrical characteristics table 14. maximum ratings rating symbol value units supply core voltage v cc -0.5 to +2.5 v maximum core operating voltage v cc +1.32 v minimum core operating voltage v cc +1.08 v
scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 electrical characteristics freescale semiconductor 22 supply i/o voltage v cc -0.5 to +4.6 v maximum i/o operating voltage v cc +3.6 v minimum i/o operating voltage v cc +3.0 v input voltage v in -0.5 to +6.0 v storage temperature range t stg -65 to150 o c table 15. operating temperature characteristic symbol value units maximum operating ambient temperature t amax 85 1 c minimum operating ambient temperature t amin -40 o c note: this published maximum operating ambient temperature s hould be used only as a system design guideline. all device operating parameters are guaranteed only when the junction temperature does not exceed 105 c. table 16. recommended operating supply voltages pin name min typ max core-vdd 1.08v 1.2v 1.32v core-vss gnd --- pad-vdd 3.0v 3.3v 3.6v pad-vss gnd advdd 3.0v 3.3v 3.6v adgnd gnd oscpad-vdd 3.0v 3.3v 3.6v oscpad-gnd gnd pllcore1vdd 1.08v 1.2v 1.32v pllcore1gnd gnd pllcore2vdd 1.08v 1.2v 1.32v pllcore2gnd gnd lin 3.0v 3.3v 3.6v table 14. maximum ratings (continued) rating symbol value units
electrical characteristics scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 freescale semiconductor 23 table 17. linear regulator operating specification characteristic symbol min typ max input voltage vin 3.0v 3.3v 3.6 output voltage (linout) vout 1.14v 1.2v 1.26v output current iout 100ma 150ma power dissipation pd 436uw load regulation 10% iout -> 90% iout 40mv 50mv 60mv power supply rejection psrr 40db note: a pmos regulator is employed as a cu rrent source in this linear regulator, so a 10f capacitor (esr 0 ... 5 ohm) is needed on the output pin (linout) to integrate the current. typically this wi ll require the use of a tantalum type capacitor.
scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 electrical characteristics freescale semiconductor 24 table 18. dc electrical specifications (i/o vcc = 3.3 vdc + 0.3 vdc) characteristic symbol min max units operation voltage range for i/o v cc 3.0 3.6 v input high voltage v ih 25.5 v input low voltage v il -0.3 0.8 v input leakage current @ 0.0 v /3.3 v during normal operation i in - 1 a hi-impedance (three-state) leakage current @ 0.0 v/3.3 v during normal operation i tsi - 1 a output high voltage i oh = 8ma 1 , 4ma 2 , 2ma 3 v oh 2.4 - v output low voltage i ol = 8ma 1 , 4ma 2 , 2ma 3 v ol -0.4 v schmitt trigger low to high threshold point 6 v t+ 1.47 - v schmitt trigger high to low threshold point 6 v t- -.95 v load capacitance (data[31:16], sclk[4:1], sclkout, ebuout[2:1], lrck[3:1], sdatao[2:1], cflg, ef, ddata[3:0], pst[3:0], pstclk, ide-dior, ide-diow, iordy) c l -50 pf load capacitance (addr[24:9], bclk) c l -40 pf load capacitance (bclke, sdcas, sdras, sdldqm, sd_cs0, sdudqm, sdwe, bufenb[2:1]) c l -30 pf load capacitance (sda0, sda1, scl0, scl1, cmd_sdio2, sdata2_bs2, sdata1_bs1, sdat a0_sdio1, cs0/cs4, cs1, oe, r/w , ta, txd[1:0], xtrim, td o/dso, rck, sfsy, subr, sdata3, tout0, qspid_out, qspics[3:0], gp[6:5]) c l -20 pf capacitance 5 , v in = 0 v, f = 1 mhz c in -6 pf data[31:16], addr[24:9], pstclk, bclk scl, sda, pst[3:0], dd ata[3:0], tdso, sdras , sdcas , sdwe , sd_cs 0, sdldqm , sdudqm, r/w tout0, rts[1:0], txd[1:0], sclk[4:1] bkpt /tms, dsi/tdi, dsclk/trst capacitance c in is periodically sampled rather than 100% tested. sclk[4:1], scl0, scl1, sda0, sda1, crin, rsti
electrical characteristics scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 freescale semiconductor 25 figure 2. clock timing definition note signals above are shown in relation to the clock. no relationship between signals is implied or intended. table 19. clock timing specification num characteristic units min max crin frequency 1 5.00 33.86 mhz c5 pstclk cycle time 7.1 ? nsec c6 pstclk duty cycle 40 60 % c7 bclk cycle time 14.2 ? nsec c8 bclk duty cycle 45 55 % note: there are only three choices for the valid audio frequencies 11.29 mhz, 16.93 mhz, or 33.86 mhz; no other values are allowed. the system clock is derived from one of these crystals via an internal pll. crin pstclk bclk c6 c6 c7 c8 c8
scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 electrical characteristics freescale semiconductor 26 table 20. input ac timing specification num characteristic units min max b1 1,2 signal valid to bclk rising (setup) 3 ? nsec b2 1 bclk rising to signal invalid (hold) 2 ? nsec b3 1 bclk to input high impedance ? 5 bclk cycle 1. inputs (rising): data[31:16] 2. ac timing specs assume 40pf load capaci tance on bclk and 50pf load capacitance on output pins. if this value is different, the i nput and output timing specifications would need to be adjusted to match the clock load. table 21. output ac timing specification num characteristic 5 units min max b10 1 bclk (8ma) rising to signal valid --- 10 nsec b11 1 bclk (8ma) rising to signal invalid (hold) 3.5 ? nsec b10 2 bclk (4ma) rising to signal valid --- 11 nsec b11 2 bclk (4ma) rising to signal invalid (hold) 4 ? nsec b12 3 bclk to high impedance (three-state) --- 14 nsec h1 hiz to high impedance ? tbd nsec h2 hiz to low impedance ? tbd nsec 1. outputs (8ma): data[31:16], addr[25,23:9] 2. outputs (4ma): sdras, sdcas, sdwe, sd_cs0, sdudqm, sdldqm, bclke 3. high impedance (three-state): data[31:16] 4. ac timing specs assume 40pf load capacitanc e on bclk and a 50pf load capacitance on output pins. if this value is different, the input and out put timing specifications would need to be adjusted to match the clock load.
electrical characteristics scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 freescale semiconductor 27 figure 3. input/outpu t timing definition-i bclk addr[24:0] r/w data[31:16] b10 b2 b5 b10 b11 b12 s0 s1 s2 s3 s4 s5 s0 s1 s2 s3 s4 s5
scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 electrical characteristics freescale semiconductor 28 figure 4. input/output timing definition-iii b13 b14 bclk h1 h2 hiz outputs outputs bclk b3 b4 inputs
electrical characteristics scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 freescale semiconductor 29 figure 5. debug timing definition table 22. debug ac timing specification num characteristic units min max d1 pstclk to signal valid (output valid) --- 6 nsec d2 pstclk to signal invalid (output hold) 1.8 ? nsec d3 1 signal valid to pstclk (input setup) 3 ? nsec d4 pstclk to signal invalid (input hold) 5 ? nsec 1. dsclk and dsi are internally synchronized. this setup time must be met only if recognition on a particular clock is required. 2. ac timing specs assume 50pf load capacita nce on pstclk and output pins. if this value is different, the input and output timing specific ations would need to be adjusted to match the clock load. pstclk dsclk dsi pst[3:0] ddata[3:0] dso d3 d1 d2 d3 d4 d4
scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 electrical characteristics freescale semiconductor 30 figure 6. timer module timing definition table 23. timer module ac timing specification num characteristic units min max t1 tin cycle time 3t ? bus clocks t2 tin valid to bclk (input setup) 6 ? nsec t3 bclk to tin invalid (input hold) 0 ? nsec t4 bclk to tout valid (output valid) ? 10 nsec t5 bclk to tout invalid (output hold) tbd ? nsec t6 tin pulse width 1t ? bus clocks t7 tout pulse width 1t ? bus clocks bclk t6 t2 t3 t1 t7 t4 t5 tin tin tout
electrical characteristics scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 freescale semiconductor 31 figure 7. uart timing definition table 24. uart module ac timing specifications num characteristic units min max u1 rxd valid to bclk (input setup) 6 ? nsec u2 bclk to rxd invalid (input hold) 0 ? nsec u3 cts valid to bclk (input setup) 6 ? nsec u4 bclk to cts invalid (input hold) 0 ? nsec u5 bclk to txd valid (output valid) --- tbd nsec u6 bclk to txd invalid (output hold) 3 ? nsec u7 bclk to rts valid (output valid) --- tbd nsec u8 bclk to rts invalid (output hold) 3 ? nsec bclk rxd cts txd rts u1 u2 u3 u4 u5 u6 u7 u8
scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 electrical characteristics freescale semiconductor 32 table 25. i2c-bus input timing specifications between scl and sda num characteristic units min max m1 start condition hold time 2 ? bus clocks m2 clock low period 8 ? bus clocks m3 scl/sda rise time (vil= 0.5 v to vih = 2.4 v) ?1 msec m4 data hold time 0 ? nsec m5 scl/sda fall time (vih= 2.4 v to vil = 0.5 v) ?1 msec m6 clock high time 4 ? bus clocks m7 data setup time 0 ? nsec m8 start condition setup time (for repeated start condition only) 2 ? bus clocks m9 stop condition setup time 2 ? bus clocks table 26. i2c-bus output timing specifications between scl and sda num characteristic units min max m1 1 start condition hold time 6 ? bus clocks m2 1 clock low period 10 ? bus clocks m3 2 scl/sda rise time (v il = 0.5 v to v ih = 2.4 v) note 2 note 2 msec m4 1 data hold time 7 ? bus clocks m5 3 scl/sda fall time (v ih = 2.4 v to v il = 0.5 v) ? 3 nsec m6 1 clock high time 10 ? bus clocks m7 1 data setup time 2 ? bus clocks m8 1 start condition setup time (for repeated start condition only) 20 ? bus clocks m9 1 stop condition setup time 10 ? bus clocks 1. note: output numbers are dependent on the value programmed into the mfdr; an mfdr programmed with the maximum frequency (mfdr = 0x20) will result in minimum output timings as shown in the above table. the mbus interface is designed to scale the actual data transition time to move it to the middle of the scl low period. the actual position is affected by the prescale and division values programmed into the mfdr; however, numbers given in t he above table are the minimum values. 2. since scl and sda are open-collector-type outputs, whic h the processor can only actively drive low, the time required for scl or sda to reach a high le vel depends on external signal capacitance and pull-up resistor values. 3. specified at a nominal 20 pf load.
electrical characteristics scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 freescale semiconductor 33 figure 8. i2c timing definition table 27. i2c output bus timings num characteristic 96 mhz units min max m10 3 scl, sda valid to bclk (input setup) 2 ? nsec m11 bclk to scl, sda invalid (input hold) 4.5 ? nsec m12 1 bclk to scl, sda low (output valid) ? 10 nsec m13 2 bclk to scl, sda inva lid (output hold) 3 ? nsec 1. since scl and sda are open-collector-type outputs, whic h the processor can only ac tively drive low, this specification applies only when scl or sda are driven low by the processor. the time required for scl or sda to reach a high level depends on external signal capacitance and pull -up resistor values. 2. since scl and sda are open-collector-type outputs, whic h the processor can only ac tively drive low, this specification applies only when scl or sda are acti vely being driven or held low by the processor. 3. scl and sda are internally synchronized.this setup ti me must be met only if recognition on a particular clock is required. m2 m6 m1 m4 m7 m8 m9 m5 m3 scl sda
scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 electrical characteristics freescale semiconductor 34 figure 9. i2c and system clock timing relationship table 28. general-purpose i/o port ac timing specifications num characteristic units min max p1 gpio valid to bclk (input setup) 6 ? nsec p2 bclk to gpio invalid (input hold) 0 ? nsec p3 bclk to gpio valid (output valid) ? tbd nsec p4 bclk to gpio invalid (output hold) 1 ? nsec bclk scl, sda in scl, sda out scl, sda out m10 m11 m12 m13
electrical characteristics scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 freescale semiconductor 35 figure 10. general-purpose parallel port timing definition table 29. ieee 1149.1 (jtag) ac timing specifications num characteristic units min max - tck frequency of operation 0 10 mhz j1 tck cycle time 100 - nsec j2a tck clock pulse high width 25 - nsec j2b tck clock pulse low width 25 - nsec j3a tck fall time (v ih =2.4 v to v il =0.5 v) ?5nsec j3b tck rise time (v il =0.5 v to v ih =2.4 v) ?5nsec j4 tdi, tms to tck rising (input setup) 8 ? nsec j5 tck rising to tdi, tms invalid (hold) 10 ? nsec j6 boundary scan data valid to tck (setup) tbd ? nsec j7 tck to boundary scan data invalid to rising edge (hold) tbd ? nsec j8 trst pulse width (asynchronous to clock edges) 12 ? nsec j9 tck falling to tdo valid (signal from driven or three-state) ?15nsec j10 tck falling to tdo high impedance ? 15 nsec j11 tck falling to boundary scan data valid (signal from driven or three-state) ? tbd nsec bclk gpio in gpio out p1 p2 p4 p3
scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 electrical characteristics freescale semiconductor 36 figure 11. jtag timing j12 tck falling to boundary scan data high impedance ? tbd nsec table 29. ieee 1149.1 (jtag) ac ti ming specifications (continued) num characteristic units min max j1 j2a j2b j4 j5 j6 j7 j8 j9 j10 j11 j12 j3a j3b tck tdi, tms trst tdo boundary scan data output boundary scan data input
electrical characteristics scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 freescale semiconductor 37 5.1 iis module ac timing specifications figure 12. sclk input, sdata output timing figure 13. sclk output, sdatao output timing diagram table 30. sclk input, sdatao output timing specifications name characteristic unit min max tu sclk fall to sdatao rise --- 25 ns td sclk fall to sdatao fall --- 25 ns table 31. sclk output, sdata0 output timing specifications name characteristic unit min max tu sclk fall to sdatao rise --- 3 ns td sclk fall to sdatao fall --- 3 ns sclk (input) sdatao1, 2 (output) tu td sclk (output) sdatao1, 2 (output) tu td
scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 pin-out and package information freescale semiconductor 38 figure 14. sclk input/output, sdatai input timing diagram 6 pin-out and package information 6.1 pinning chart table 32. sclk input, sdatai input timing specifications name characteristic unit min max tsu sdatai in to sclkn -5 ? ns th sclk rise to sdatai 3 ? ns table 33. 144 qfp pin assignments 144 qfp pin number name type description pin state after reset 01 data16 i/o data x 02 a23/gpo54 i/o sdram address / static adr out (requires pull up /down for boot-up selection) 03 pad-vdd 04 a22 o sdram address / static adr out 05 a21 o sdram address / static adr out 06 a20/a24 o sdram address / static adr out 07 a19 o sdram address / static adr out 08 a18 o sdram address / static adr out sclk sdata1, 3, 4 (input) tsu th ( inp ut or output )
pin-out and package information scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 freescale semiconductor 39 09 pad-gnd 10 a17 o sdram address / static adr out 11 a16 o sdram address / static adr out 12 a15 o sdram address / static adr out 13 a14 o sdram address / static adr out 14 a13 o sdram address / static adr out 15 pad-vdd 16 a12 o sdram address / static adr out 17 a11 o sdram address / static adr out 18 core-vdd 19 core-gnd 20 a10 o sdram address / static adr out 21 a9 o sdram address / static adr out 22 a8 o sdram address / static adr out 23 a7 o sdram address / static adr out 24 a6 o sdram address / static adr out 25 a5 o sdram address / static adr out 26 pad-gnd pad-gnd 27 a4 o sdram address / static adr out 28 a3 o sdram address / static adr out 29 a2 o sdram address / static adr out 30 a1 o sdram address / static adr out 31 cs0/cs4 o static chip select 0 / static chip select 4 out 32 rw o bus write enable out 33 osc pad vdd 34 crin i crystal / external clock input x table 33. 144 qfp pin assignments (continued) 144 qfp pin number name type description pin state after reset
scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 pin-out and package information freescale semiconductor 40 35 crout o crystal clock output x 36 osc pad gnd osc_pad_gnd 37 pll core1 vdd 38 pll core2 vdd 39 pll core2 gnd 40 pll core1 gnd 41 oe o output enable out 42 ide-diow/gpio32 i/o ide diow out / high 43 ide-iordy/gpio33 i/o ide interface iordy in / low 44 ide-dior/gpio31 i/o ide interface dior out / high 45 bufenb2/gpio30 i/o external buffer 2 enable out / high 46 bufenb1/gpio29 i/o external buffer 1 enable out / high 47 ta/gpio12 i/o transfer acknowledge in (requires pull-up for normal operation) 48 wake_up/ gpio21 i/o wake-up input in (requires pull-up for normal operation) 49 ebuin2/sclk_out/ gpio13 i/o audio interfaces ebu in 2 / flashmedia clock in / low 50 ebuin3/cmd_sdio2/ gpio14 i/o audio interfaces ebu in 3 / flashmedia command interface in / low 51 pad vdd 52 ebuin1/gpio36 i/o audio interfaces ebu in 1 in / low 53 ebuout1/gpio37 i/o audio inte rfaces ebu out 1 out / low 54 xtrim/gpio0 i/o audio interfaces x-tal trim out / clock out 55 cs1/qspi_cs3/gpio28 i/o chip select 1/ qspi chip select 3 out / high 56 rck/ qspi_din/qspi_dout/ gpio26 i/o subcode rck interface / qspi data in / data out out / low table 33. 144 qfp pin assignments (continued) 144 qfp pin number name type description pin state after reset
pin-out and package information scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 freescale semiconductor 41 57 qspi_clk/subr/ gpio25 i/o qspi clock pin / subcode interface out / low 58 qspi_dout/sfsy/ gpio27 i/o qspi data output / subcode interface sfsy out / low 59 qspi_cs1/ebuout2/ gpio16 i/o qspi chip select 1 output / audio interface ebu output 2 out / low 60 qspi_cs0/ebuin4/ gpio15 i/o qspi chip select 0 / audio interface ebuin 4 out / low 61 pad gnd 62 sclk1/gpio20 i/o audio interfaces serial clock 1 in / low 63 lrck1/gpio19 i/o audio interfaces word clock 1 in / low 64 sdatao1/tout0/ gpio18 i/o audio interfaces serial data output 1 / timer output 0 out / low 65 sdatai1/gpio17 i audio interfaces serial data in 1 in / low 66 cflg/gpio5 i/o cflg input in / low 67 ef/gpio6 i/o error flag input in / low 68 qspi_cs2/mclk2/ gpio24 i/o qspi chip select output 2 / audio master clock output 2 out / low 69 sdatai3/gpio8 i/o audio interfaces serial data input 3 in / low 70 adin0/gpi52 a ad input 0 in only 71 adin1/gpi53 a ad input 1 in only 72 adin2/gpi54 a ad input 2 in only 73 advdd 74 adgnd 75 adin3/gpi55 a ad input 3 in only 76 adin4/gpi56 a ad input 4 in only 77 adin5/gpi57 a ad input 5 in only 78 adref a adc reference input in 79 adout/sclk4/ gpio58 i/o ad output / sclk4 (for gpi function in low power applications) out / clock output table 33. 144 qfp pin assignments (continued) 144 qfp pin number name type description pin state after reset
scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 pin-out and package information freescale semiconductor 42 80 lrck3/gpio43/ audio_clock i/o audio interface lrck3 / audio master clock input in / low 81 sclk3/gpio35 i/o audio interface sclk3 in / low 82 scl0/sdata1_bs1/ gpio41 i/o i2c0 clock line / flashmedia data interface out / low 83 sda0/sdata3/ gpio42 i/o i2c0 data / flashmedia data interface hi-z 84 ddata0/cts1/ sdata0_sdio1/ gpio1 i/o debug / uart1 cts / flashmedia data interface out / high 85 ddata1/rts1/ sdata2_bs2/gpio2 i/o debug / uart1 rts / flashmedia data interface out / high 86 ddata2/cts0/gpio3 i/o debug / uart0 cts out / high 87 ddata3/rts0/gpio4 i/o debug / uart0 rts out / high 88 scl1/txd1/gpio10 i/o i2c1 clock line / second uart transmit data output out / low 89 core vdd 90 core gnd 91 sda1/rxd1/gpio44 i/o i2c1 data line / second uart receive data input hi-z 92 pad vdd 93 txd0/gpio45 i/o first uart transmit data output out / high 94 rxd0/gpio46 i/o first uart receive data input in / low 95 pst3/intmon1/ gpio47 i/o debug / interrupt monitor output 1 out / high 96 pst2/intmon2/ gpio48 i/o debug / interrupt monitor output 2 out / high 97 pad gnd 98 pst1/gpio49 i/o debug out / high 99 pst0/gpio50 i/o debug out / high 100 pstclk/gpio51 i/o debug out / clock output 101 tdo/dso o jtag/debug bdm table 33. 144 qfp pin assignments (continued) 144 qfp pin number name type description pin state after reset
pin-out and package information scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 freescale semiconductor 43 102 tdi/dsi i jtag/debug bdm 103 tck i jtag bdm 104 tms/bkpt i jtag/debug bdm 105 trst/dsclk i jtag/debug bdm 106 rsti i reset x 107 sclk2/gpio22 i/o audio interfaces serial clock 2 in / low 108 lrck2/gpio23 i/o audio interfaces ebu out 1 in /low 109 linout a linear regulator output x 110 linin a linear regulator input x 111 lingnd linear regulator ground x 112 sdatao2/gpio34 i/o audio interfaces serial data output 2 out / low 113 mclk1/gpio11 i/o audio master clock output 1 out / clock output 114 hi-z i jtag x 115 test2 i test x 116 test1 i test x 117 test0 i test x 118 sdwe/gpio38 i/o sdram write enable out / high 119 sdcas/gpio39 i/o sdram cas out / high 120 pad vdd 121 sdras/gpio59 i/o sdram ras out / high 122 sd_cs0/gpio60 i/o sdram chip select out 0 out / high 123 sdldqm/gpo52 o sdram ldqm out / high 124 sdudqm/gpo53 o sdram udqm out / high 125 bclke/gpio63 i/o sdram clock enable output out / high 126 bclk/gpio40 i/o sdram clock output out / high 127 data31 i/o data x 128 data30 i/o data x table 33. 144 qfp pin assignments (continued) 144 qfp pin number name type description pin state after reset
scf5250 integrated coldfire? micr oprocessor data sheet, rev. 1.1 pin-out and package information freescale semiconductor 44 6.2 package the scf5250 is assembled in 144-pin qfp package. thermal characteristic s are not available at this time. 129 pad gnd 130 data29 i/o data x 131 data28 i/o data x 132 data27 i/o data x 133 data26 i/o data x 134 data25 i/o data x 135 pad-vdd 136 data24 i/o data x 137 data23 i/o data x 138 data22 i/o data x 139 data21 i/o data x 140 data20 i/o data x 141 pad gnd 142 data19 i/o data x 143 data18 i/o data x 144 data17 i/o data x table 33. 144 qfp pin assignments (continued) 144 qfp pin number name type description pin state after reset
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